ASIC Digital Design Sr Staff Engineer - Verification
SynopsysHo Chi Minh City, Vietnam
Posted November 13, 2025
Full Time
About the Company
Synopsys drives the innovations that shape the way we live and connect, leading in chip design, verification, and IP integration.
Job Description
Job Title ASIC Digital Design Sr Staff Engineer - Verification, developing reusable verification environments and testbenches using UVM, ensuring functionality and quality of industry-leading silicon chips, accelerating delivery of reliable ASIC and SoC products.
Requirements
- Minimum 6 years’ SoC/ASIC verification experience
- Strong SystemVerilog (UVM preferred) skills
- Expertise in assertions-based and constraint random verification
- Experience with coverage-driven verification and HVP
- Scripting skills: Perl, Tcl, csh, or Python
- Familiarity with VCS and Verdi tools
Benefits
- Comprehensive range of health, wellness, and financial benefits