ASIC Digital Design, Sr Staff Engineer - Verification
SynopsysViet Nam, Ho Chi Minh
Posted December 22, 2025
Full Time
About the Company
Synopsys drives the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.
Job Description
We are seeking a passionate and experienced ASIC Digital Design Engineer with a strong background in design verification to join our Digital and Verification Development team. As a Sr Staff Engineer, you will be responsible for planning tests, checklists, coverage, and assertion planning, and creating detailed verification environments from functional specifications. You will apply advanced verification techniques and write test cases, checkers, and coverage that implement the verification test plan. You will participate in technical reviews, contribute actively, and provide customer support with the bring-up of IP in customer simulation environments.
Requirements
- BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications
- 8+ years of experience in design verification
- Strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal)
- Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus
- Proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus