ASIC Digital Design Verification, Staff Engineer

We are seeking an enthusiastic and detail-oriented ASIC Digital Design Verification Engineer to join our team at Synopsys. As a Staff Engineer, you will be responsible for designing and implementing verification environments, collaborating with design and architecture teams, and mentoring junior engineers. You will have a strong understanding of digital design and verification methodologies, and be proficient in using advanced verification tools and techniques.

Requirements

• Proficiency in digital design and verification methodologies
• Experience with developing testbenches using System Verilog and UVM
• Expertise in using advanced verification techniques
• Familiarity with scripting languages such as Python or Perl for automation
• Strong understanding of digital design and verification concepts
• Excellent problem-solving skills and attention to detail

Benefits

• Competitive salary and benefits package
• Opportunities for professional growth and development
• Collaborative and dynamic work environment
• Recognition and rewards for outstanding performance