We are seeking a seasoned Principal Engineer with 12+ years of experience in Analog and Mixed Signal Layout to lead our AMS layout team. The successful candidate will have expertise in transistor-level custom layout, advanced CMOS/FinFET nodes, and precision analog layout techniques. The role will involve architecting complex floorplans, applying advanced matching techniques, shielding/guard ring strategies, parasitic-aware routing, and reliability-driven design practices.
Requirements
- Bachelor's or Master's degree in Electrical Engineering or related field
- 12+ years of experience in Analog and Mixed Signal Layout, ideally with deep SerDes / AMS IP ownership
- Expertise in complete AMS layout flow from device placement through GDS sign-off, including matching, shielding, guard rings, isolation, dummy insertion, and parasitic-aware layout
- Deep knowledge of CMOS, FinFET, and advanced process technologies; strong understanding of LDE, process design rules, and device physics
- Strong proficiency with custom layout EDA tools including Synopsys Custom Compiler, Cadence Virtuoso, and foundry tech files
- Understanding of reliability concepts (EM, IR, ESD, LUP) and their application to high-speed AMS circuits
- Strong problem-solving, root-cause analysis, and debugging capability with extracted views and silicon correlation
- Experience leading layout teams, mentoring talent, and owning major IP from concept to tapeout
- Familiarity with scripting (Skill/Python/Tcl) is a plus
- Experience delivering high-volume production silicon is preferred
- Passion for continuous learning, methodology enhancement, and advancing layout excellence
Benefits
- Competitive salary
- Comprehensive benefits package
- Opportunities for professional growth and development