Synopsys is a technology leader in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
Synopsys is seeking a Sr Supervisor, Layout Design to lead the development of next-generation DDR/HBM IP layouts, drive technical innovation and quality excellence, and mentor and manage a team of layout engineers. The ideal candidate will have 8+ years of relevant experience in layout design and team management, proficiency in deep submicron effects and advanced floorplan techniques, and expertise in layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, and IO frame and pitch requirements.
Synopsys is a technology leader in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.