Staff Logic Design Engineer

Teledyne LeCroy is seeking a Staff Logic Design Engineer to join their high-speed Protocol Team. The successful candidate will architect and implement high-performance digital logic for protocol capture, analysis, and emulation, collaborating with cross-functional teams to deliver industry-leading solutions.

Requirements

• BS in EE, CS or Computer Engineering required
• 7+ years of experience in digital logic design for FPGA or ASIC
• Strong proficiency in Verilog/SystemVerilog RTL design
• Experience with one or more of the following protocols: PCIe, CXL, NVMe, USB, SAS, SATA