Staff, Design for Test Engineer (DFT)

Tenstorrent is looking for a Design for Test Engineer to join their team. The role involves implementing DFT features into RTL, understanding DFT architectures, and working on various IPs on the chip. The work is collaborative and requires strong problem-solving skills.

Requirements

• Implementation of DFT features into RTL using verilog.
• Understanding of DFT Architectures and micro-architectures.
• ATPG and test coverage analysis using industry standard tools.
• JTAG, Scan Compression, and ASST implementation.
• Gate level simulation using Synopsys VCS and Verdi.
• Support silicon bring-up and debug.
• MBIST planning, implementation, and verification.
• Support Test Engineering on planning, patterns, and debug.
• Develop efficient DFx flows and methodology compatible with front end and physical design flows

Benefits

• highly competitive compensation package and benefits
• equal opportunity employer