PhD Position in High-Performance CMOS Phase-Locked Loop Design

Join the ERC Synergy DISRUPT project to reinvent PLL architectures for next-generation wireless communication. Design ultra-low-jitter, low-spur PLLs and validate them on real silicon.

Requirements

• M.Sc. degree in Microelectronics, Electrical Engineering, or a closely related field.
• Strong background in analog, mixed-signal, and RF circuit design.
• Hands-on RTL design experience (SystemVerilog, Verilog, or Verilog-AMS).
• Demonstrable creativity and originality in problem solving and circuit design.
• Good presentation, writing, and communication skills.
• Strong command of English (spoken and written).
• Ability to work effectively in an international and collaborative research environment.
• Strong team player with excellent communication skills to collaborate smoothly with international colleagues.

Benefits

• Salary and benefits are in accordance with the Collective Labour Agreement for Dutch Universities
• TU Delft Graduate School provides an inspiring research environment
• Flexible work schedules can be arranged
• TU Delft offers a customisable compensation package, discounts on health insurance, and a monthly work costs contribution