SoC/ASIC Design Verification Engineer

zeroRISC is redefining chip security and supply chain integrity by empowering device owners and operators in crucial sectors like silicon production, IoT, and critical infrastructure with full device ownership, control, and visibility.

Requirements

• Verify ASIC/SoC functionality, performance, security, and power throughout the full chip design life cycle, from test plan definition to sign-off
• Build high quality verification environments at the chip/top and block levels following engineering best practices
• Write thorough verification documentation including test plans
• Diagnose, debug, and resolve regression failures and other errors
• Achieve coverage closure
• Ensure design functionality while upholding stringent timelines in collaboration with architecture, design, software, system, and silicon validation teams as well as engineering program managers

Benefits

• Directly contribute to the development of cutting-edge security solutions, protecting critical systems in industrial and IoT environments
• Significant opportunities for learning and career growth as a seed-stage startup
• Join a close-knit, innovative team where you can learn, grow, and contribute to building something meaningful in the security space