Design Verification Engineer

Role Overview

Design Verification Engineer will collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans. They will develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).

What You Will Do

Develop verification components, including drivers, monitors, scoreboards, and checkers. Execute simulation regressions, debug test failures, analyze root causes, and work with designers to implement corrective measures.

Why It Might Be a Fit

The ideal candidate will have 3+ years of experience in ASIC or FPGA design verification, expertise in Hardware Description Languages (HDL) like Verilog or VHDL and Hardware Verification Languages (HVL) such as SystemVerilog, and strong hands-on experience in developing UVM-based testbenches and verification components.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• 3+ years of experience in ASIC or FPGA design verification
• Expertise in Hardware Description Languages (HDL) like Verilog or VHDL and Hardware Verification Languages (HVL) such as SystemVerilog
• Strong hands-on experience in developing UVM-based testbenches and verification components
• Proficiency in modern verification methodologies, including coverage-driven verification (CDV) and assertion-based verification (ABV)
• Familiarity with industry-standard protocols such as AMBA (AXI, ACE, CHI, APB), PCIe, or Ethernet
• Experience with simulation and debug tools
• Strong scripting skills in Python, Perl, or Tcl for automation and data analysis
• Excellent analytical, problem-solving, and debugging skills
• Strong communication skills and the ability to work effectively in a collaborative, cross-functional team environment