Cellular SoC Static Timing Analysis Engineer

We are seeking an ASIC STA Engineer to join our world class modem team. As an ASIC STA Engineer, you will be responsible for all aspects of timing including working with designers for timing constraints generation, helping construct/modify flows, timing analysis and timing closure. You will have responsibilities spanning various aspects of SOC design: full chip and block level timing closure ownership throughout the entire project, generation of block and full chip timing constraints, and own timing sign-off to make sure timing requirements are met across all corners, modes, and conditions.

Requirements

• BS and 3+ years of relevant industry experience
• Hands-on experience in ASIC timing constraints generation and timing closure
• Good knowledge in STA tools (such as Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing
• Good understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and BIST testing
• Own STA sign-off for block and chip level including custom timing checks
• Hands on experience in timing/SDC constraints generation and management
• Knowledge of low-power techniques including clock gating, power gating and multi-voltage designs
• Proficient in scripting languages (Tcl and Perl/Python)
• Strong communication skills are a pre-requisite as the candidate will collaborate with a lot of different groups (e.g. digital design, DFT, physical design, etc.)