Cellular SoC Static Timing Analysis Engineer

We are seeking a Cellular SoC Static Timing Analysis Engineer to join our world-class modem team. As an ASIC STA Engineer, you will be responsible for all aspects of timing, including timing constraints generation, timing analysis, and timing closure. You will work closely with various multi-functional teams to resolve sophisticated timing issues and own timing sign-off to ensure timing requirements are met across all corners, modes, and conditions.

Requirements

• BS and 10+ years of relevant industry experience
• Hands-on experience in ASIC timing constraints generation and timing closure
• Expertise in STA tools (such as Primetime) and methodologies for timing closure
• Strong background in Constraint analysis and debug
• Proficient in scripting languages (Tcl and Perl/Python)
• Strong communication skills