Timing & Synthesis Engineer

Join Apple's wireless silicon development team as a Timing & Synthesis Engineer. Work on developing Wireless SoCs with custom hardware accelerators and multiple processor sub-systems, improving processes and collaborating with multi-disciplinary groups.

Requirements

• Bachelors degree and 3+ years of relevant industry experience
• Timing constraint (SDC) creation at partition and chip level
• Logic synthesis execution (verilog RTL to netlist)
• Strong knowledge of the entire ASIC design process
• Expertise in STA tools and flow
• UPF usage for power and voltage islands
• Knowledge of timing corners, operating modes, process variation and signal integrity-related issues
• Skilled in scripting languages (TCL, PERL, Python)
• Proficient in the closure of end-to-end logic equivalence (FV, LEC) with functional ECOs in the mix
• Familiarity with DFT approaches and constraints
• Proficient with RTL Verilog/VHDL
• Familiarity with digital top integration flows/methodology/checks

Benefits

• On-site location
• Full-time position