FE Design and Timing Engineer

Join Apple's growing wireless silicon development team and work on high performance, low power wireless SoCs from RTL to delivery of final GDSII. Collaborate with multi-disciplinary groups to meet power, performance, and area goals for Apple's products.

Requirements

• BS degree
• 3+ years of relevant industry experience
• Knowledge of ASIC design flow, synthesis, static timing analysis, and RTL to Post Synthesis netlist
• Experience with industry standard Timing, Logic Equivalence, Physical Design, and Synthesis tools
• Proficiency in scripting in TCL, Perl, or Python
• Knowledge of SoC Architecture and HDL languages like Verilog/System Verilog
• Hands-on experience in timing/SDC constraints generation, analysis, and management
• Knowledge of timing corners, operating conditions, process variations, and signal integrity-related issues
• Knowledge of Place and Route steps including floor planning, CTS, Routing, and timing ECOs
• Understanding of UPF and low-power design and implementation techniques
• Understanding of DFT methodologies including Scan and BIST