FE Design and Timing Engineer

Join Apple's growing wireless silicon development team and work on implementing high-performance, low-power wireless SoCs from RTL to delivery of final GDSII. Collaborate with multi-disciplinary groups to meet power, performance, and area goals for Apple's products.

Requirements

• BS degree and minimum 10 years of relevant industry experience
• Knowledge of ASIC design flow, synthesis, static timing analysis, RTL to Post Synthesis netlist
• Exposure to industry standard Timing, Logic Equivalence, Physical Design and Synthesis tools
• Proficient in scripting in TCL, Perl or Python
• Knowledge of basic SoC Architecture and HDL languages like Verilog / System Verilog