Design Verification Engineer, Staff

Astera Labs is seeking a Staff Design Verification Engineer to contribute to the functional verification of cutting-edge AI connectivity ASICs using SystemVerilog, UVM, and problem-solving skills.

Requirements

• Bachelor's degree in Electrical Engineering; Master's preferred
• 5+ years of experience verifying and validating complex SoCs for Server, Storage, and/or Networking applications
• Strong proficiency with SystemVerilog/UVM-based verification methodologies
• Experience developing test plans, test sequences, and coverage closure strategies
• Knowledge of industry-standard simulators, revision control systems, and regression systems
• Ability to work independently and collaboratively with cross-functional teams

Benefits

• Base salary range $160,000 to $195,000
• Discretionary bonus, incentives and benefits