Principal Design Verification Engineer
Astera LabsSan Jose, California, United States
Posted March 12, 2026
185000 - 230000 USD
Full Time
About the Company
Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions.
Job Description
Astera Labs is seeking a Principal Design Verification Engineer to develop innovative verification strategies for next-generation AI connectivity ASICs. The successful candidate will leverage their expertise in SystemVerilog, UVM, and hybrid verification methodologies to ensure high-quality silicon.
Requirements
- Bachelor's degree in Electrical Engineering; Master's preferred
- 10+ years of experience verifying and validating complex SoCs for Server, Storage, and/or Networking applications
- Expert-level proficiency with SystemVerilog/UVM-based verification methodologies
- Proven ability to develop and execute test plans, stimulus generation, and coverage closure strategies
- Experience with industry-standard simulators, revision control systems, and regression infrastructure
- Strong debugging skills with ability to work independently and collaboratively with design teams
Benefits
- Discretionary bonus, incentives and benefits