Principal Design Verification Engineer

Astera Labs is seeking a Principal Design Verification Engineer to lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.

Requirements

• Bachelor’s degree in Electrical Engineering (Master’s preferred)
• 8+ years of experience in SoC verification, particularly for server and networking applications
• Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle
• Proficiency with industry-standard simulators, version control, and regression systems
• Strong debugging and coverage analysis skills
• Experience developing and executing test sequences, generating stimuli, and identifying verification holes
• Familiarity with verification of switching architectures, including packet processing and forwarding engines
• Excellent communication skills and ability to work independently with minimal supervision

Benefits

• Discretionary bonus, incentives, and benefits