Physical Design Chip Top Expert

Astera Labs is seeking a Physical Design Chip Top Expert to lead chip-level PD execution with full SoC CoT end-to-end engineering chip development (RTL to GDS). The ideal candidate will have 15+ years of experience in chip top physical design/backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below).

Requirements

• B.Sc. or M.Sc. in Electrical Engineering
• 15+ years of hands-on experience in Chip Top Physical Design/Backend
• Proven experience in leading teams or projects with a 'can-do' approach and excellent communication skills
• Deep expertise in Chip Top Level activities and signoff
• Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)
• Experience managing both complex Macro-level designs subsystem level and Full-Chip integration

Benefits

• Competitive salary
• Stock options
• Health insurance
• Retirement plan
• Paid time off
• Relocation assistance