Physical Design Subsystem (Multiple IP’s/Partitions) Lead

Astera Labs is seeking a Physical Design Subsystem (Multiple IP’s/Partitions) Lead to help build its local engineering powerhouse in Israel. This role will involve building and mentoring a high-performing team, owning the end-to-end execution from Synthesis to Signoff, and leading the transition from RTL to GDS.

Requirements

• B.Sc. or M.Sc. in Electrical Engineering
• 15+ years of hands-on experience in Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below)
• Proven experience in leading teams or projects with a 'can-do' approach and excellent communication skills
• Deep expertise in RTL2GDS flows, including P&R, STA, Physical verification (DRC/LVS), Formal verification, low-power implementation (UPF/CPF), EMIR and evaluating foundry process nodes and third-party IPs
• Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)
• Experience managing both complex Macro-level designs subsystem level and Full-Chip integration