Senior/ Staff Chip Top Physical Design Engineer

Astera Labs is seeking a highly skilled Chip Top Physical Design Engineer to join their local engineering powerhouse in Israel. The role involves executing the physical design of the SoC Top level for chips that drive the world’s largest AI clusters, ensuring silicon meets extreme performance, power, and area (PPA) targets required for AI scale.

Requirements

• B.Sc. or M.Sc. in Electrical Engineering
• 5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below)
• Deep hands-on expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR
• Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus)
• Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration