Lead Design Engineer

Lead Design Engineer position based in Bangalore, involved in ASIC design verification, test plan creation, and post-silicon validation.

Requirements

• Strong expertise in Verilog, HVL(SV/Specman e) with UVM/OVM/eRM methodology
• Experience in functional coverage/code coverage/assertions development and closure
• Experience in test plan creation
• Exposure to PCIe and LPDDR verification
• Strong debug skills

Benefits

• Generous Paid Time Off
• 401k Matching
• Retirement Plan