
Job description
The Principal Post-Silicon Validation Engineer will be responsible for leading the validation of Marvell's PCIe Gen 6, Gen 7, and High-speed Serdes product lines. This role will involve defining, documenting, executing, and reporting the overall PHY validation/test plan for Marvell storage devices. The engineer will also be responsible for lab-based silicon bring-up and unit test execution, as well as performing high-speed signal validation and analysis.
The engineer will be responsible for leading electrical validation of high-speed signal products, performing high-speed signal validation and analysis, and analyzing and debugging issues on Phy protocol of storage interface (PCIe, Ethernet). They will also troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers, and work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues.
The ideal candidate will have a strong understanding of high-speed SERDES, equalization technique, and PCIe protocols, as well as 5+ years of experience with High Speed IO testing, debugging, and validation. They will also have strong lab skills, analytical, problem-solving, and communication skills.
Company

Tech, Software & IT Services
Marvell is a global semiconductor company that designs and manufactures advanced infrastructure solutions for connectivity, storage, and data center workloads. Its portfolio spans wireless and wired connectivity, enterprise and consumer solutions, cloud infrastructure, and high-performance storage. Marvell differentiates itself through an end-to-end design approach that integrates silicon, software, and services, enabling partners to accelerate product development and achieve superior performance. The company emphasizes collaborative engineering, agile partnerships, and a culture that prioritizes execution and innovation, fostering a workplace where employees collaborate closely with customers to deliver tailored solutions.
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