Systems and Validation Lead/Manager

The Systems Engineering Manager will be responsible for validation and qualification of electrical interfaces and/or performing standards-based protocol tests.

Requirements

• 8+ years of systems hardware development and debug experience
• Deep knowledge of signal integrity and power integrity design practices
• Knowledge of at least 2 of electrical interfaces for any of the high-speed protocols
• Knowledge of inter-chip protocols, such as UART, I2C, I3C, SPI, I2S, PWM
• Ability to develop test scripts that control test equipment for determining IC device characteristics
• Familiarity with Verilog
• Software development and debugging experience in C, C++, and Python and other scripting languages
• Experience in creating and simulating models of wired links and being able to make appropriate tradeoffs

Benefits

• Opportunity to work with a team of validation and characterization engineers
• Chance to design characterization test, system-level test, and demonstration systems
• Mentorship and leadership opportunities