Verification Engineering Lead/Manager

Designing, developing, and deploying UVM based Testbenches for multi-core processor subsystems with emphasis on verifying and signing off performance, power, and functionality. Leading a team of Verification engineers and managing tasks to achieve tape out and production goals.

Requirements

• BS in EE with 3+ years of experience or MS in EE with 1+ year experience
• Strong knowledge of digital design and two or three of AMBA AHB/AXI/APB based SoC Architecture, ADC/DAC, PCIe, Ethernet, CAN, LPDDR interfaces
• Strong knowledge of Verilog, System Verilog, UVM, C/C++
• Experience in usage of assertions, constrained random generation, functional/code coverage
• Knowledge of scripting languages like Perl, Python, TCL, Linux shells to achieve automation of verification methodologies and flows
• Analytical debugging skills
• Excellent team building and management skills

Benefits

• Developing testbenches for AMS and FC simulations
• Developing tests to get 95+% coverage for the simulations
• Working with Design team to debug any failures
• Integrating and running the BIST and DFT gate level sims.
• Running daily and weekly regressions and publishing results
• Responsible for FC RTL, Gate level simulations
• Mentoring and leading a team of Verification engineers
• Working with Systems and Test engineering team to help validate the parts and release them to production