Verification Engineering Lead/Manager

The position involves designing, developing and deploying UVM based Testbenches for multi-core, multi-threaded processor subsystems. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM/RISC-V processor technology.

Requirements

• BS in EE with 8+ years of experience or MS in EE with 6+ year experience
• Strong knowledge of digital design and two or three of AMBA AHB/AXI/APB based SoC Architecture, ADC/DAC, PCIe, Ethernet, CAN, LPDDR interfaces.
• Experience managing a verification team
• Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/Siloti
• Fluent in verification languages such as UVM/OVM/System Verilog, Vera, Verilog
• Experience in writing Test-plans and creating directed and random test cases
• Strong scripting skills in Perl, Python, Linux shells etc.
• Strong problem-solving skill to quickly identify and provide solution under tight schedule pressure
• Strong analytical problem solving and attention to details
• Team player with interest in filing up gaps in product development as needed
• Good written and verbal communication skills
• Good technical documentation skills
• Good interpersonal skills, self-motivated, self-starter

Benefits

• Leadership opportunity
• Mentorship and team management experience
• Opportunity to work with ASIC Simulation Tool & Verification Language
• Experience in writing Test-plans and creating directed and random test cases