ASIC Digital Design, Staff Engineer

We are seeking an enthusiastic engineer to lead and drive ownership of critical areas of verification in our ASIC Digital Design team. As a Staff Engineer, you will be responsible for defining, implementing, and tracking comprehensive verification test plans to ensure robust coverage and quality for our Subsystem. You will also be responsible for coding and debugging test cases, extracting and reviewing functional coverage metrics, and working closely with RTL designers and architects to ensure functional correctness.

Requirements

• Bachelor's or Master's degree in electronics/electrical engineering or related field
• 8+ years' experience in ASIC/FPGA Verification
• Ability to debug and define robust verification strategies
• Experience mentoring is a plus for senior candidates
• Demonstrated experience in technically leading a team
• Proven expertise in developing System Verilog/UVM based test environments for complex ASIC designs
• Advanced skills in developing and implementing rigorous test plans, checkers, assertions, and coding complex tests
• Strong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage
• Experience with interface protocols and IP design/verification processes; knowledge of DDR/HBM/PCIe/UCIe/Ethernet/UALink is highly desirable

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Total rewards include both monetary and non-monetary offerings
• Salary range and benefits will be discussed during the hiring process