ASIC Digital Design, Staff Engineer

We are seeking an enthusiastic engineer who thrives at the intersection of various interface IPs to join our Subsystem organization. The ideal candidate will have a keen analytical mindset, a collaborative spirit, and a growth mindset, with a commitment to excellence and technical rigor. The role involves leading and driving ownership of critical areas of verification, defining and implementing comprehensive verification test plans, and coding and debugging test cases. The successful candidate will enable the successful verification and deployment of high-performance Subsystem in leading-edge SoCs worldwide and drive quality that powers AI, automotive, cloud, and mobile applications at massive scale.

Requirements

• Bachelor's or Master's degree in electronics/electrical engineering or related field
• 8+ years' experience in ASIC/FPGA Verification
• Ability to debug and define robust verification strategies
• Proven expertise in developing System Verilog/UVM based test environments for complex ASIC designs
• Strong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage
• Experience with interface protocols and IP design/verification processes
• Hands-on experience in owning end-to-end verification deliverables for IPs, including planning, execution, DV metrics closure, and review/signoff

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Total rewards include both monetary and non-monetary offerings