ASIC Verification- Staff Engineer

At Synopsys, we drive the innovations that shape the way we live and connect. We are seeking an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions.

Requirements

• BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification
• Expertise in developing HVL (System Verilog)-based verification environments and testbenches
• Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools
• Proficiency in verification methodologies such as UVM, OVM, or VMM
• Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB
• Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog)
• Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Total rewards include both monetary and non-monetary offerings