Synopsys is a global leader in engineering solutions that span the entire silicon‑to‑system lifecycle, empowering customers to accelerate the development of AI‑powered products. The company delivers cutting‑edge silicon design, semiconductor IP, electronic design automation (EDA), and simulation and analysis tools, complemented by professional design services. Synopsys distinguishes itself through deep industry partnerships that enhance R&D productivity and unlock innovative capabilities across technology sectors. Its commitment to software quality and security further ensures reliable, high‑performance solutions for complex electronic systems.
We are looking for a Staff Engineer to join our DesignWare IP Verification R&D team. The ideal candidate will have expertise in ASIC or IP verification, experience with System Verilog and industry-standard verification methodologies, and a strong analytical mindset. You will be responsible for specifying, architecting, and implementing advanced verification environments for DesignWare IP cores and working closely with cross-functional and multi-site teams.
Synopsys is a global leader in engineering solutions that span the entire silicon‑to‑system lifecycle, empowering customers to accelerate the development of AI‑powered products. The company delivers cutting‑edge silicon design, semiconductor IP, electronic design automation (EDA), and simulation and analysis tools, complemented by professional design services. Synopsys distinguishes itself through deep industry partnerships that enhance R&D productivity and unlock innovative capabilities across technology sectors. Its commitment to software quality and security further ensures reliable, high‑performance solutions for complex electronic systems.