Staff ASIC RTL Design Engineer

Staff ASIC RTL Design Engineer at Synopsys: Design and implement state-of-the-art RTL designs for the DesignWare IP family, leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field
• 4+ years of hands-on industry experience in ASIC RTL design
• Deep expertise in data path and control path design
• Proficiency in synthesizable Verilog/SystemVerilog
• Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler
• Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell)
• Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI)
• Exposure to quality processes in IP design and verification is an advantage
• Prior experience as a technical lead or mentor is highly desirable

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Total rewards include both monetary and non-monetary offerings