Principal RTL Design Engineer

Role Overview

As a Principal RTL Design Engineer, you will lead and contribute to the design and delivery of Core Subsystem across multiple SoC generations. You will work with systems architects and microarchitects to define high-level, implementable SOC specifications and own end-to-end IP/Sub-system RTL delivery.

What You Will Do

Your responsibilities will include collaborating with cross-functional teams, leading RTL design and integration of Sub-system, and driving the development of robust Safety, Security, and Debug architectures for advanced SOCs.

Why It Might Be a Fit

We are looking for a candidate with deep experience in RTL design and SoC-level integration, strong proficiency with frontend flows, and excellent leadership and communication skills.

Requirements

• Bachelor's or Master's degree or equivalent experience in Electronics/Electrical Engineering
• 15+ years of RTL design experience
• Hands on experience in RTL coding, debugging, verification, synthesis and timing closure
• Strong experience in ARM based SOC architecture and ASIC design flow
• AMBA protocols (AXI, AHB, APB), clock/reset domains and memory sub-systems
• Experience with EDA tools for synthesis, LINT, CDC, RDC and timing analysis
• Familiarity with formal verification techniques, static/dynamic power checks
• Proficiency in scripting and automation using Python
• Excellent leadership, communication skills
• Experience working with global cross-functional teams
• Working knowledge of safety-critical design flows in automotive systems

Benefits

• Diverse and inclusive workplace
• Equity in career development, career opportunities, and equal remuneration
• Opportunities for growth and learning
• Global Top Employer certification
• Recognition for ethics & integrity, purpose & values, organization & change, business strategy, and performance