Principal RTL Design Engineer

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. You will work on next-generation IP and processor subsystems where your decisions shape products that power everything from automotive systems to AI accelerators.

Requirements

• BTech or MTech in Electrical or Electronics Engineering
• 6+ years of hands-on experience in ASIC or SoC design with RTL development and tape-out delivery
• Deep expertise in Verilog and SystemVerilog, with working knowledge of UPF and clock gating techniques
• Proven experience with Spyglass, VCLP, Design Compiler, and PrimeTime in real design flows
• Solid understanding of at least one processor architecture such as ARM, RISC-V, x86, or MIPS
• Hands-on scripting ability in Python or Perl to automate checks and manage design data

Benefits

• Comprehensive range of health, wellness, and financial benefits