Lead RTL Design Engineer

Lead RTL Design Engineer at Synopsys, driving innovations in high-performance silicon IPs, collaborating across multidisciplinary teams to deliver robust, scalable, and innovative products.

Requirements

• B.E./M.E. in Electrical/Computer Engineering or equivalent
• 8+ years of experience in RTL design for IP, ASIC, or SoC
• Expertise in Verilog/SystemVerilog RTL coding, synthesis, CDC, and DFT concepts

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Total rewards include both monetary and non-monetary offerings