Lead RTL Design Engineer, IP Development

Lead RTL Design Engineer, IP Development job at Synopsys in Bengaluru, India. The role involves architecting and implementing RTL for high-speed Ethernet IP cores, translating protocol specifications, and leading design tasks. The successful candidate will have a decade of experience in building RTL that ships in silicon and a strong command of synthesizable Verilog or SystemVerilog RTL coding.

Requirements

• Bachelor's or Master's in Electrical Engineering with 10+ years of hands-on ASIC digital design experience
• Deep knowledge of at least one industry protocol: Ultra Accelerator Link, Ethernet, DDR, PCIe, or USB
• Proven experience architecting control path logic including asynchronous FIFOs, DMA architectures, and SPRAM/DPRAM interfaces
• Strong command of synthesizable Verilog or SystemVerilog RTL coding with experience across lint, CDC, synthesis, formal checking, and static timing analysis
• Hands-on experience closing timing on designs running at 600MHz or higher, experience with Fusion Compiler is a significant plus
• Proficiency with Perforce and scripting in Perl or Shell, prior experience leading or mentoring designers is a major plus

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Total rewards include both monetary and non-monetary offerings