Sr RTL Design Engineer

Senior RTL Design Engineer position at Synopsys in Bhubaneswar, India. We're looking for a passionate and driven RTL Design Engineer who thrives on translating complex specifications into robust, reusable, and high-performance digital hardware. You will own and develop IP-level microarchitecture and synthesizable RTL for advanced on-chip PVT sensing and telemetry subsystems, define detailed microarchitecture/specifications, and implement reusable, high-quality RTL that meets functional and performance goals. You will also perform rigorous static checks, drive synthesis, and collaborate closely with DV, PD, and DFT teams for integration and sign-off.

Requirements

• 2–5 years hands-on experience in RTL design, microarchitecture, and IP integration using Verilog
• Expertise in static checks: Lint and CDC analysis with tools such as SpyGlass, Questa, or Real Intent
• Proficiency in synthesis and static timing analysis (STA) using DC/Genus and PrimeTime/Tempus; LEC sign-off using Formality/Conformal
• Solid understanding of clock/reset architectures, clock domain crossing, FIFOs, and handshake mechanisms
• Experience with AMBA protocols (AXI, AHB, APB) and SoC-level integration flows